This invention relates in general to digital data processing and more specifically to a uniform interface for transferring digital information to and from a computational unit in an adaptive computing engine (ACE) architecture.
A common limitation to processing performance in a digital system is the efficiency and speed of transferring data and other information among different components and subsystems within the digital system. For example, the bus speed in a general-purpose Von Neumann architecture dictates how fast data can be transferred between the processor and memory and, as a result, places a limit on the computing performance (e.g., million instructions per second (MIPS), floating-point operations per second (FLOPS), etc.).
Other types of computer architecture design, such as multi-processor or parallel processor designs require complex communication, or interconnection, capabilities so that each of the different processors can communicate with other processors, with multiple memory devices, input/output (I/O) ports, etc. With today's complex processor system designs, the importance of an efficient and fast interconnection facility rises dramatically. However, such facilities are difficult to design to optimize goals of speed, flexibility and simplicity of design. Also, a uniform interconnection, or interface, is desirable to reduce the overall complexity of a system, improve programmability and to reduce design and manufacturing costs.